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hsdl-3220 irda ? data compliant low power 4.0 mbit/s infrared transceiver data sheet description the hsdl-3220 is a new generation low profile high speed infrared transceiver module that provides interface between logic and ir signals for through- air, serial, half-duplex ir data-link. the module is fully compliant to irda physical layer specification version 1.4 low power from 9.6kbit/s to 4.0 mbit/s (fir) and is iec825-class 1 eye safe. the hsdl-3220 can be shutdown completely to achieve very low power consumption. in the shutdown mode, the pin diode will be inactive and thus pro- ducing very little photocurrent even under very bright ambient light. it is also designed to interface to input/ output logic circuits as low as 1.8v. these features are ideal for mobile devices that require low power consumption. features ? fully compliant to irda 1.4 physical layer low power specification from 9.6 kbit/s to 4.0 mbit/s (fir) ? miniature package C height: 2.5 mm C width: 8.0 mm C depth: 3.0 mm ? typical link distance > 50 cm ? guaranteed temperature performance, -25 o to 70 o c ? critical parameters are guaranteed over temperature and supply voltage ? low power consumption C low shutdown current C complete shutdown of txd, rxd, and pin diode ? excellent emi performance ? vcc supply 2.7 to 3.6 volts ? interfacing with i/o logic circuits as low as 1.8 v ? lead-free package ? led stuck-high protection ? designed to accommodate light loss with cosmetic windows ? iec 825-class 1 eye safe ? lead-free and rohs compliant applications ? mobile telecom C mobile phones C smart phones C pagers ? data communication C pocket pc handheld products C personal digital assistants C portable printers ? digital imaging C digital cameras C photo-imaging printers ? electronic wallet ? small industrial & medical instrumentation C general data collection devices C patient & pharmaceutical data collection devices figure 1. functional block diagram of hsdl-3220. figure 2. rear view diagram with pinout. 1 2 3 4 5 6 7 8 transmitter hsdl-3220 cx1 cx2 cx4 sd (5) rxd (4) v cc v cc (6) iov cc (7) gnd (8) v led r1 cx3 txd (3) led c (2) led a (1) receiver shield
2 order information part number packaging type package quantity HSDL-3220-021 tape and reel front view 2500 hsdl-3220-001 tape and reel front view 500 i/o pins configuration table pin symbol description i/o type notes 1 led a led anode i 1 2 led c led cathode 2 3 txd transmit data. active high. i 3 4 rxd receive data. active low. o 4 5 sd shutdown. active high. i 5 6 vcc supply voltage 6 7 iovcc input/output asic vcc 7 8 gnd ground 8 - shield emi shield 9 marking information the unit is marked with the letter g and ywwll on the shield where: y is the last digit of the year ww is the work week ll is the lot information recommended application circuit components component recommended value notes r1 5.6 ? 5%, 0.25 watt for 2.7 vled < 3.3v 10 ? 5%, 0.25 watt for 3.3 vled < 4.2v 15 ? 5%, 0.25 watt for 4.2 vled < 5.5v cx1, cx4 0.47 f 20%, x7r ceramic 10 cx2, cx3 6.8 f 20%, tantalum 11 notes: 1. tied through external series resistor, r1, to regulated vled from 2.7 to 5.5v. please refer to table above for recommended series resistor value. 2. internally connected to led driver. leave this pin unconnected. 3. this pin is used to transmit serial data when sd pin is low. if this pin is held high for longer than 50 s, the led is turned off. do not float this pin. 4. this pin is capable of driving a standard cmos or ttl load. no external pull-up or pull-down resistor is required. the pin is in tri-state when the transceiver is in shutdown mode. the receiver output echoes transmitted signal. 5. the transceiver is in shutdown mode if this pin is high for more than 400 s. on falling edge of this signal, the state of the txd pin sampled and used to set receiver low bandwidth (txd=low) or high bandwidth (txd=high) mode. refer to the section bandwidth selection timing for programming information. do not float this pin. 6. regulated, 2.7 to 3.6 volts. 7. connect to asic logic controller vcc voltage or supply voltage. the voltage at this pin must be equal to or less than supply voltage. 8. connect to system ground. 9. connect to system ground via a low inductance trace. for best performance, do not connect directly to the transceiver pin gnd. 10. cx1 must be placed within 0.7 cm of the hsdl-3220 to obtain optimum noise immunity. 11. in environments with noisy power supplies, including cx2, as shown in figure 1, can enhance supply ripple rejection performance. application support information the application engineering group is available to assist you with the application design associated with the hsdl-3220 infrared transceiver module. you can contact them through your local sales representatives for additional details.
3 bandwidth selection timing the transceiver is in default sir/ mir mode when powered on. user needs to apply the following programming sequence to both the sd and txd inputs to enable the transceiver to operate at fir mode. setting the transceiver to sir/mir mode (9.6 kbit/s to 1.152 mbit/s) 1. set sd/mode input to logic high 2. txd input should remain at logic low 3. after waiting for t s 25 ns, set sd/mode to logic low, the high to low negative edge transition will determine the receiver bandwidth 4. ensure that txd input re- mains low for t h 100 ns, the receiver is now in sir/mir mode 5. sd input pulse width for mode selection should be > 50 ns. setting the transceiver to fir (4.0 mbit/s) mode 1. set sd/mode input to logic high v ih 50% t s t h v il 50% 50% txd sd/mode v il v ih 50% t s t h v il 50% 50% txd sd/mode v ih v il figure 3. bandwidth selection timing at sir/mir mode. figure 4. bandwidth selection timing at fir mode. transceiver i/o truth table inputs outputs txd light input to receiver sd led rxd note high dont care low on not valid low high low off low 12,13 low low low off high dont care dont care high off high notes: 12. in-band irda signals and data rates 4.0 mbit/s 13. rxd logic low is a pulsed response. the condition is maintained for a duration dependent on pattern and strength of the inci dent intensity. 2. after sd/mode input remains high at > 25 ns, set txd input to logic high, wait t s 25 ns (from 50% of txd rising edge till 50% of sd falling edge) 3. then set sd/mode to logic low, the high to low negative edge transition will determine the receiver band- width 4. after waiting for t h 100 ns, set the txd input to logic low 5. sd input pulse width mode selection should be > 50 ns.
4 absolute maximum ratings for implementations where case to ambient thermal resistance is 50 c/w. parameter symbol min. max. units conditions s torage temperature t s -40 +100 c operating temperature t a -25 +70 c led anode voltage v leda 0 6.5 v supply voltage v cc 0 6.5 v input voltage: txd, sd/mode v i 0 6.5 v output voltage: rxd v o 0 6.5 v dc led transmit current i led (dc) 50 ma average transmit current i led (pk) 200 ma 90 s pulse width 25% duty cycle recommended operating conditions parameter symbol min. typ. max. units conditions supply voltage v cc 2.7 3.6 v input/output voltage iovcc 1.8 vcc v logic input voltage logic high v ih iov cc C 0.5 iov cc v for txd, sd/mode logic low v il 0 0.4 v logic high e ih, min 0.0081 mw/cm 2 9.6kbit/s in-band signals 1.152 mbit/s [14] receiver input irradiance 0.020 mw/cm 2 1.152 mbit/s < in-band signals 4.0 mbit/s [14] e ih, max 500 mw/cm 2 9.6 kbit/s in-band signals 4.0 mbit/s [14] logic low e il 0.3 w/cm 2 for in-band signals [14] led (logic high) current i leda 150 ma pulse amplitude receiver data rate 0.0096 4.0 mbit/s note : 14. an in-band optical signal is a pulse/sequence where the peak wavelength, p, is defined as 850 p 900 nm, and the pulse characteristics are compliant with the irda serial infrared physical layer link specification v1.4. cautions: the bicmos inherent to the design of this component increases the component s susceptibility to damage from electrostatic discharge (esd). it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd.
5 electrical and optical specifications specifications (min. and max. values) hold over the recommended operating conditions unless otherwise noted. unspecified test conditions may be anywhere in their operating range. all typical values (typ.) are at 25 c, vcc set to 3.0v and iovcc set to 1.8v unless otherwise noted. parameter symbol min. typ. max. units conditions receiver viewing angle 2 30 peak sensitivity wavelength p 880 nm rxd output voltage logic high v oh iov cc C 0.2 iov cc vi oh = -200 a, ei 0.3 w/cm 2 logic low v ol 0 0.4 v i ol = 200 a, ei 8.1 w/cm 2 rxd pulse width (sir) [15] t pw (sir) 1 4.0 s 15 , c l = 9 pf rxd pulse width (mir) [16] t pw (mir) 100 500 ns 15 , c l = 9 pf rxd pulse width (fir) [16] t pw (fir) 80 175 ns 15 , c l = 9 pf rxd rise and fall times t r , t f 60 ns c l = 9 pf receiver latency time [17] t l 25 50 s receiver wake up time [18] t w 50 100 s transmitter radiant intensity ie h 10 45 mw/sr i leda = 150 ma, 15 , v txd v ih , v sd v il , ta=25 c viewing angle 2 30 60 peak wavelength p 875 nm spectral line half width ? 35 nm txd input current high i h 10 av txd v ih low i l 10 a0 v txd v il led on current i leda 150 ma v txd v ih , r1=5.6ohm, vled=3.0v txd pulse width (sir) t pw (sir) 1.5 1.6 1.8 st pw (txd) = 1.6 s at 115.2 kbit/s txd pulse width (mir) t pw (mir) 148 217 260 ns t pw (txd) = 217 ns at 1.152 mbit/s txd pulse width (fir) t pw (fir) 115 125 135 ns t pw (txd)=125 ns at 4.0 mbit/s maximum optical pw [19] t pw(max.) 50 100 s txd rise and fall time (optical) t r , t f 600 ns t pw (txd) = 1.4 s at 115.2 kbit/s 40 ns t pw (txd) = 125 ns at 4.0 mbit/s led anode on-state voltage v on(leda) 1.6 2.1 v i leda =150 ma, v txd v ih transceiver supply current shutdown i cc1 0.1 1 av sd v ih, ta= 25 c idle i cc2 1.8 3.0 ma v sd v il , v txd v il , ei=0 notes: 15. for in-band signals from 9.6 kbit/s to 115.2 kbit/s, where 9 w/cm 2 ei 500 mw/cm 2 . 16. for in-band signals from 0.576 mbit/s to 4.0 mbit/s, where 22.5 w/cm 2 ei 500 mw/cm 2 . 17. latency time is defined as the time from the last txd light output pulse until the receiver has recovered full sensitivity. 18. receiver wake up time is measured from vcc power on or sd pin high to low transition to a valid rxd output. 19. the maximum optical pw is the maximum time the led remains on when the txd is constantly high. this is to prevent long turn on time of the led for eye safety protection.
6 figure 5. rxd output waveform. figure 6. led optical waveform. figure 8. receiver wakeup time waveform. figure 7. txd stuck on protection waveform. t f v oh 90% 50% 10% v ol t pw t r t f led off 90% 50% 10% led on t pw t r t pw (max.) txd led rx light t rw rxd sd figure 9. radiant intensity vs i leda . i leda (a) radiant intensity (mw/sr) 0.10 0.20 0.15 0.30 0.35 0.25 120 100 80 60 40 20 0 figure 10. v leda vs i leda . i leda (a) v leda (v) 0.10 0.20 0.15 0.30 0.35 0.25 2.4 2.2 2.0 1.8 1.6 1.4
7 hsdl-3220 package dimensions 2.0 0.4 0.8
8 hsdl-3220 tape and reel dimensions note: the carrier tape is compliant to the packaging materials standards for esd sensitive device, eia-541 unit: mm 1.75 0.1 7.5 0.1 16.0 0.2 8.0 0.1 8.4 0.1 4.0 0.1 1.5 0.1 3.4 0.1 progressive direction 2.8 0.1 0.4 0.05 polarity ?1.5 +0.1 0 pin 8: vled pin 1: gnd empty (40 mm min) parts mounted leader (400 mm min) empty (40 mm min) unit: mm label detail a option # "b" 178 60 quantity 500 001 330 80 2500 021 "c" 13.0 0.5 2.0 0.5 21 0.8 r1.0 detail a 2.0 0.5 16.4 +2 0 bc
9 moisture proof packaging all hsdl-3220 options are shipped in moisture proof package. once opened, moisture absorption begins. figure 11. baking conditions chart. units in a sealed moisture-proof package package is opened (unsealed) environment less than 30 c, and less than 60% rh package is opened less than 72 hours perform recommended baking conditions no baking is necessary yes no no yes baking conditions if the parts are not stored in dry conditions, they must be baked before reflow to prevent damage to the parts. package temp. time in reels 60 c 48 hours in bulk 100 c 4 hours 125 c 2 hours 150 c 1 hour baking should only be done once. recommended storage conditions storage temperature 10 c to 30 c relative humidity below 60% rh time from unsealing to soldering after removal from the bag, the parts should be soldered within three days if stored at the recom- mended storage conditions. this part is compliant to jedec level 4.
10 recommended reflow profile process zone symbol ? t maximum ? t/ ? time heat up p1, r1 25 c to 160 c4 c/s solder paste dry p2, r2 160 c to 200 c 0.5 c/s solder reflow p3, r3 200 c to 255 c (260 c at 10 seconds max) 4 c/s p3, r4 255 c to 200 c-6 c/s cool down p4, r5 200 c to 25 c-6 c/s the reflow profile is a straight- line representation of a nominal temperature profile for a convec- tive reflow solder process. the temperature profile is divided into four process zones, each with different ? t/ ? time temperature change rates. the ? t/ ? time rates are detailed in the above table. the temperatures are measured at the component to printed circuit board connections. in process zone p1 , the pc board and hsdl-3220 castellation pins are heated to a temperature of 160 c to activate the flux in the solder paste. the temperature ramp up rate, r1, is limited to 4 c per second to allow for even heating of both the pc board and hsdl-3220 castellations. process zone p2 should be of sufficient time duration (60 to 120 seconds) to dry the solder paste. the temperature is raised to a level just below the liquidus point of the solder, usually 200 c (392 f). process zone p3 is the solder reflow zone. in zone p3, the temperature is quickly raised above the liquidus point of solder to 255 c (491 f) for optimum results. the dwell time above the liquidus point of solder should be between 20 and 60 seconds. it usually takes about 20 seconds to assure proper coalescing of the solder balls into liquid solder and the formation of good solder connections. beyond a dwell time of 60 seconds, the intermetallic growth within the solder connec- tions becomes excessive, result- ing in the formation of weak and unreliable connections. the temperature is then rapidly reduced to a point below the solidus temperature of the solder, usually 200 c (392 f), to allow the solder within the connections to freeze solid. process zone p4 is the cool down after solder freeze. the cool down rate, r5, from the liquidus point of the solder to 25 c (77 f) should not exceed 6 c per second maximum. this limitation is necessary to allow the pc board and hsdl-3220 castellations to change dimensions evenly, putting minimal stresses on the hsdl-3220 transceiver. 0 t-time (seconds) t C temperature C ( c) 230 200 160 120 80 50 150 100 200 250 30 0 180 220 255 p1 heat up p2 solder paste dry p3 solder reflow p4 cool down 25 r1 r2 r3 r4 r5 60 sec. max. above 220 c max. 260 c
11 appendix a: smt assembly application note solder pad, mask and metal stencil aperture figure 12. stencil and pcba. figure 13. stencil and pcba. recommended land pattern metal stencil for solder paste printing land pattern pcb stencil aperture solder mask 0.60 1.75 0.10 0.475 1.425 c l mounting center fiducia l shield solder pad 0.775 2.05 2.375 3.325 unit: mm 1.25 1.35
12 recommended metal solder stencil aperture it is recommended that only a 0.152 mm (0.006 inches) or a 0.127 mm (0.005 inches) thick stencil be used for solder paste printing. this is to ensure adequate printed solder paste volume and no shorting. see the table below the drawing for combinations of metal stencil aperture and metal stencil thickness that should be used. aperture opening for shield pad is 2.7 mm x 1.25 mm as per land pattern. apertures as per land dimensions l w t adjacent land keepout and solder mask areas adjacent land keep-out is the maximum space occupied by the unit relative to the land pattern. there should be no other smd components within this area. the minimum solder resist strip width required to avoid solder bridging adjacent pads is 0.2 mm. it is recommended that two fiducial crosses be place at mid- length of the pads for unit alignment. note: wet/liquid photo- imageable solder resist/mask is recommended. stencil thickness, t (mm) aperture size (mm) length, l width, w 0.152 mm 2.60 0.05 0.55 0.05 0.127 mm 3.00 0.05 0.55 0.05 figure 14. solder stencil aperature. figure 15. adjacent land keepout and solder mask areas. 0.2 3.0 10.1 solder mask 3.85 units: mm
13 appendix b: pcb layout suggestion the following pcb layout guide- lines should be followed to obtain a good psrr and em immunity resulting in good electrical performance. things to note: 1. the ground plane should be continuous under the part, but should not extend under the shield trace. 2. the shield trace is a wide, low inductance trace back to the system ground. cx1, cx2, cx3, and cx4 are optional supply filter capacitors; they may be left out if a clean power supply is used. 3. vled can be connected to either unfiltered or unregu- lated power supply. if vled and vcc share the same power supply, cx3 need not be used and the connections for cx1 and cx2 should be before the current limiting resistor r1. in a noisy environment, including capacitor cx2 can enhance supply rejection. cx1 is generally a ceramic capacitor of low inductance providing a wide frequency response while cx2 and cx3 are tantalum capacitors of big volume and fast frequency response. the use of a tantalum capacitor is more critical on the vled line, which carries a high current. cx4 is an optional ceramic capacitor, similar to cx1, for the iovcc line. figure 16. pcb layout suggestion. top layer connect the metal shield and module ground pin to bottom ground layer. layer 2 critical ground plane zone. do not connect directly to the module ground pin. layer 3 keep data bus away from critical ground plane zone. bottom layer (gnd) the area underneath the module at the second layer, and 3 cm in all directions around the module is defined as the critical ground plane zone. the ground plane should be maximized in this 4. preferably a multi-layered board should be used to provide sufficient ground plane. use the layer under- neath and near the transceiver zone. refer to application note an1114 or the agilent irda data link design guide for details. the layout below is based on a 2-layer pcb. module as vcc, and sandwich that layer between ground connected board layers. refer to the diagram below for an example of a 4 layer board.
14 description the hsdl-3220, a low-cost and small form factor infrared trans- ceiver, is designed to address the mobile computing market such as pdas, as well as small-embedded mobile products such as digital cameras and cellular phones. it is fully compliant to irda 1.4 low power specification from 9.6 kbit/s to 4.0 mbit/s, and supports hp-sir and tv remote modes. the design of the hsdl- 3220 also includes the following unique features: ? low passive component count. ? shutdown mode for low power consumption requirement. ? interface to input/output logic circuits as low as 1.8v selection of resistor r1 resistor r1 should be selected to provide the appropriate peak pulse led current over different ranges of vcc as shown in the table below. transceiver mod/ de-modulator speaker rf interface audio interface user interface microcontroller dsp core asic controller ir microphone hsdl-3220 figure 17. mobile phone platform. minimum peak pulse recommended r1 vcc intensity led current 5.6 ? 3.0 v 45 mw/sr 150 ma interface to recommended i/o chips the hsdl-3220 s txd data input is buffered to allow for cmos drive levels. no peaking circuit or capacitor is required. data rate from 9.6 kbit/s up to 4.0 mbit/s is available at the rxd pin. the block diagram below shows how the ir port fits into a mobile phone and pda platform. appendix c: general application guide for the hsdl-3220
15 lcd panel hsdl-3220 touch panel com port rs232c driver pcmcia controller rom ram cpu for embedded application ir figure 18. pda platform. the link distance testing was done using typical hsdl-3220 units with smc s fdc37c669 and fdc37n769 super i/o controllers. an ir link distance of up to 50 cm was demonstrated for sir and fir speeds.
16 appendix d: window designs for hsdl-3220 d z k a ir transparent window opaque material opaque material ir transparent window x y figure 19. window design diagram. optical port dimensions for hsdl-3220 to ensure irda compliance, some constraints on the height and width of the window exist. the minimum dimensions ensure that the irda cone angles are met without vignetting. the maxi- mum dimensions minimize the effects of stray light. the mini- mum size corresponds to a cone angle of 30 and the maximum size corresponds to a cone angle of 60 . in the figure below, x is the width of the window, y is the height of the window and z is the distance from the hsdl-3220 to the back of the window. the distance from the center of the led lens to the center of the photodiode lens, k, is 5.1mm. the equations for computing the window dimensions are as follows: x = k + 2 * (z+d) * tana y = 2 * (z+d) * tana the above equations assume that the thickness of the window is negligible compared to the distance of the module from the back of the window (z). if they are comparable, z' replaces z in the above equation. z' is defined as z' = z + t/n where t is the thickness of the window and n is the refractive index of the window material. the depth of the led image inside the hsdl-3220, d, is 3.17 mm. a is the required half angle for viewing. for irda compliance, the minimum is 15 and the maximum is 30 . assum- ing the thickness of the window to be negligible, the equations result in the following tables and graphs.
17 module depth aperture width (x, mm) aperture height (y, mm) (z) mm max. min. max. min. 0 8.76 6.80 3.66 1.70 1 9.92 7.33 4.82 2.33 2 11.07 7.87 5.97 2.77 3 12.22 8.41 7.12 3.31 4 13.38 8.94 8.28 3.84 5 14.53 9.48 9.43 4.38 6 15.69 10.01 10.59 4.91 7 16.84 10.55 11.74 5.45 8 18.00 11.09 12.90 5.99 9 19.15 11.62 14.05 6.52 aperture width (x) ? mm 25 module depth (z) ? mm 10 47 0 09 15 26 20 5 13 5 8 aperture width (x) vs. module depth x max. x min. aperture height (y) ? mm 16 module depth (z) ? mm 8 47 0 09 10 26 4 13 5 8 aperture height (y) vs. module depth 14 12 6 2 y max. y min. figure 20. aperture width (x) vs. module depth. figure 21. aperture height (y) vs. module depth.
18 window material almost any plastic material will work as a window material. polycarbonate is recommended. the surface finish of the plastic should be smooth, without any texture. an ir filter dye may be used in the window to make it look black to the eye, but the total optical loss of the window should be 10% or less for best optical performance. light loss should be measured at 875 nm. the recommended plastic materials for use as a cosmetic window are available from general electric plastics. shape of the window from an optics standpoint, the window should be flat. this ensures that the window will not alter either the radiation pattern of the led, or the receive pattern of the photodiode. if the window must be curved for mechanical or industrial design reasons, place the same curve on the back side of the window that has an identical radius as the front side. while this will not completely eliminate the lens effect of the front curved surface, it will significantly reduce the effects. the amount of change in the radiation pattern is depen- dent upon the material chosen for the window, the radius of the front and back curves, and the distance from the back surface to the transceiver. once these items are known, a lens design can be made which will eliminate the effect of the front surface curve. the following drawings show the effects of a curved window on the radiation pattern. in all cases, the center thickness of the window is 1.5 mm, the window is made of polycarbonate plastic, and the distance from the transceiver to the back surface of the window is 3 mm. recommended plastic materials: material # light transmission haze refractive index lexan 141 88% 1% 1.586 lexan 920a 85% 1% 1.586 lexan 940a 85% 1% 1.586 note : 920a and 940a are more flame retardant than 141. figure 22. shape of windows. curved front and back (second choice) flat window (first choice) curved front, flat back (do not use)
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies, limited in the united states and other countries. data subject to change. copyright ? 2006 avago technologies, limited. all rights reserved. obsoletes 5989-3140en 5989-3640en august 29, 2006

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